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Assume we have a system with CPU which is fully compatible with Intel 8259 Programmable Interrupt Controller. So, this CPU use vectored interrupts, of course.

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When one of eight interrupts occurs, PIC just asserts INTR wire that is connected to the CPU. Now PIC waits for CPU until INTA will be asserted. When so, PIC selects interrupt with the highest priority (depends on pin number), and then send its interrupt vector to data bus. I omitted some timing, but it doesn't matter for now, I think.

Here are questions:

• How whole device, that causes interrupt, knows that his interruptrequest was accepted and it can pull off interrupt request? I read about 8259, but I didn't find it.
• Is acknowledge device, whose interrupt was accepted, performed in ISR?

Sorry for my English.

Nik NovákNik Novák

2 Answers

The best reference is the original intel doc and is available here: https://pdos.csail.mit.edu/6.828/2012/readings/hardware/8259A.pdf It has full details of these modes, how the device operates, and how to program the device.

Caveat: I'm a bit rusty as I haven't programmed the 8259 in many years, but I'll take a shot at explaining things, per your request.

After an interrupting device, connected to an IRR ['interrupt request register'] pin, has asserted an interrupt request, the 8259 will convey this to the CPU by assserting INTR and then placing the vector on the bus during the three INTA cycles generated by the CPU.

After a given device has asserted IRR, the 8259's IS ['in-service'] register is or'ed with a mask of the IRR pin number. The IS is a priority select. While the IS bit is set, other interrupting devices of lower priority [or the original one] will not cause an INTR/INTA cycle to the CPU. The IS bit must be cleared first. These interrupts remain 'pending'.

The IS can be cleared by an EOI (end-of-interrupt) operation. There are multiple EOI modes that can be programmed. The EOI can be generated by the 8259 in AEOI mode. In other modes, the EOI is generated manually by the ISR by sending a command to the 8259.

The EOI action is all about allowing other devices to cause interrupts while the ISR is processing the current one. The EOI does not clear the interrupting device.

Clearing the interrupting device must be done by the ISR using whatever device specific register the device has for that purpose. Usually, this a 'pending interrupt' register [can be 1 bit wide]. Most H/W uses two interrupt related registers and the other one is an 'interrupt enable' register.

With level triggered interrupts, if the ISR does not clear the device, when the ISR does issue the EOI command to the 8259, the 8259 will [try to] reinterrupt the CPU using the vector for the same device for the same condition. The CPU will probably be reinterrupted as soon as it issues an sti or iret instruction. Thus, an ISR routine must take care to process things in proper sequence.

Consider an example. We have a video controller that has four sources for interrupts:

HSTART -- start of horizontal line
HEND -- end of horizontal line [start of horizontal blanking interval]
VSTART -- start of new video field/frame
VEND -- end of video field/frame [start of vertical blanking interval]

The controller presents these as a bit mask in its own special interrupt source register, which we'll call vidintr_pend. We'll call the interrupt enable register vidintr_enable.

The video controller will use only one 8259 IRR pin. It is the responsibility of the CPU's video ISR to interrogate the vidpend register and decide what to do.

The video controller will assert its IRR pin as long as vidpend is non-zero. Since we're level triggered, the CPU may be re-interrupted.

Here is a sample ISR routine to go with this:

UPDATE:

Your followup questions:

1. Why do you use interrupt disable on video controller register instead of mask 8259's interrupt enable bit?
2. When you execute vidisr_nested(void) function, it will enable nesting the same interrupt. Is it true? And is that what you want?

To answer (1), we should do both but not necessarily in the same place. They seem similar, but work in slightly different ways.

We change the video controller registers in the video controller driver [as it's the only place that 'understands' the video controller's registers].

The video controller actually asserts the 8259's IRR pin from: IRR = ((vidintr_enable & vidintr_pend) != 0). If we never set vidintr_enable (i.e. it's all zeroes), then we can operate the device in a 'polled' [non-interrupt] mode.

The 8259 interrupt enable register works similarly, but it masks against which IRRs [asserted or not] may interrupt the CPU. The device vidintr_enable controls whether it will assert IRR or not.

In the example video driver, the init routine enables the vertical interrupts, but not the horizontal. Only the vertical interrupts will generate a call to the ISR, but the ISR can/will also process the horizontal ones [as polled bits].

Changing the 8259 interrupt enable mask should be done in a place that understands the interrupt topology of the entire system. This is usually done by the containing OS. That's because the OS knows about the other devices and can make the best choice.

Herein, 'containing OS' could be a full OS like Linux [of which I'm most familiar]. Or, it could just be an R/T executive [or boot rom--I've written a few] that has some common device handling framework with 'helper' functions for the device drivers.

For example, although it's usual that all devices get their own IRR pin. But, it is possible, with level triggering, for two different devices to share an IRR. (e.g.) IRR[0] = devA_IRROUT | devB_IRROUT. Either through an OR gate [or wired OR(?)].

It's also possible that the device is attached to a 'nested' or 'cascaded' interrupt controller. IIRC [consult document], it is possible to have a 'master' 8259 and [up to] 8 'slave' 8259s. Each slave 8259 connects to an IRR pin of the master. Then, connect devices to the slave IRR pins. For a fully loaded system, you can have 256 interrupting devices. And, the master can have slave 8259s on some IRR pins and real devices on others [a 'hybrid' topology].

Usually, only the OS knows enough to deal with this. In a real system, a device driver probably wouldn't touch the 8259 at all. The non-specific EOI would probably have been sent to the 8259 before entering the device's ISR. And, the OS would handle the full 'save state' and 'restore state' and the driver just handles device specific actions.

Also, under an OS, the OS will call the 'init' and 'stop' routines. The general OS routines for this will handle the 8259 and call the device specific ones.

For example, under Linux [or almost any other OS or R/T executive], the interrupt sequence goes something like this:

To answer (2), yes, you are correct. It would probably interrupt immediately, and might nest (infinitely :-).

The simple ISR version is more efficient and preferable if the actions taken in the ISR are short, quick, and simple (e.g. just output to a few data ports).

If the required actions take a relatively long time (e.g. do intensive calculations, or write to a large number of ports or memory locations), the nested version is preferred to prevent other devices from having entry to their ISRs delayed excessively.

However, some time critical devices [like a video controller] need to use the simple model, preventing interruption by other devices, to guaranteed that they can complete in a finite, deterministic time.

For example, the video ISR handling of VEND might program the device for the next/upcoming field/frame and must complete this within the vertical blanking interval. They, have to do this, even if it means 'excessive' delay of other ISRs.

Note that the ISR was 'racing' to complete before the end of the blanking interval. Not the best design. I've had to program such a controller/device. For rev 2, we changed the design so the device registers were double-buffered.

That meant that we could set up the registers for frame 1 anytime during the [much longer] frame 0 display period. At VSTART for frame 1, the video hardware would instantly clock-in/save the double-buffered values, and the CPU could then setup for frame 2 anytime during the display of frame 1. And so on ...

With the modified design, the video driver removed the device setup from the ISR entirely. It was now handled from OS task level

In the driver example, I've adjusted the sequencing a bit to prevent infinite stacking, and added some additional information based upon my question (1) answer. That is, it shows [crudely] what to do with or without an OS.

BTW, I'm the author of the linux irqtune program

I wrote it back in the mid 90's. It's of lesser use now, and probably doesn't work on modern systems, but the FAQ I wrote has a great deal of information about interrupt device priorities. The program itself did a simple 8259 manipulation.

An online copy is available here: http://archive.debian.org/debian/dists/Debian-1.1/main/disks-i386/SpecialKernels/irqtune/README.html There's probably source code somewhere in this archive.

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That's the version 0.2 doc. I haven't found an online copy of version 0.6 which has better explanation, so I've put up a text version here: http://pastebin.com/Ut6nCgL6

Side note: The 'where to get' information in the FAQ [and email address] are no longer valid. And, I didn't understand the full impact of 'spam' until I posted the FAQ and starting getting [tons of] it ;-)

And, irqtune even drew Linus' ire. Not because it didn't work but because it did: https://lkml.org/lkml/1996/8/23/19 IMO, if he had read the FAQ, he would have understood why [as what irqtune did is standard stuff to R/T guys].

UPDATE #2

Your new questions:

3. I think that you are missing a destination address in write_port(8259_interrupt_enable &= ~VIDEO_IRR_PIN). Isn't it so?
4. IRR register is read-only or r/w? If the second case, what is the purpose of writing into it?
5. Interrupt vectors are stored as logical addresses or physical address?

To answer question (3): No, not really [even if it seemed so]. The code snippet was 'pseudo code' [not pure C code], as I mentioned in a code comment at the top, so technically speaking, I'm covered. However, to make it more clear, here is what the [closer to] real C code would look like:

Now, in video_init, replace the code inside STANDALONE with video_enable(1), and, in video_stop with video_enable(0)

As to question (4): We weren't really writing to the IRR, even though the symbol had _IRR_ in it. As mentioned in the code comments above, we were writing to the 8259 interrupt enable register which is really the 'interrupt mask register' or IMR in the documentation. The IMR can be read from and written to by using OCW1 (see doc).

There is no way for software to access the IRR at all. (i.e.) There is no port in the 8259 to read or write the IRR value. The IRR is completely internal to the 8259.

There is a one-to-one correspondence between IRR pin numbers [0-7] and IMR bit numbers (e.g. to enable for IRR(0), set IMR bit 0), but the software has to know which bit to set.

Because the video controller is physically connected to a given IRR pin, it is always the same for a given PC board. The software [on older non-PnP systems] can't probe for this. Even on newer systems, the 8259 knows nothing of PnP, so it's still hardwired. The video controller driver programmer must just 'know' what IRR pin is being used [by consulting the 'spec sheet' or controller 'architecture reference manual'].

To answer question (5): First consider what the 8259 does.

When the 8259 is intialized, the ICW2 ('initialization command word 2') gets set by the OS driver. This defines a portion of interrupt vector number the 8259 will present during the INTR/INTA cycle. In ICW2, the most significant 5 bits are marked T7-T3.

When an interrupt occurs, these bits are combined with the IRR pin number of the interrupting device [which is 3 bits wide] to form an 8 bit interrupt vector number: T7,T6,T5,T4,T3|I2,I1,I0

For example, if we put 0xD0 into ICW2, with our video controller using IRR pin 3, we'd have 1,1,0,1,0|0,1,1 or 0xD3 as the interrupt vector number that the 8259 will send to the CPU.

This is just a vector number [0x00-0xFF] as the 8259 knows nothing of memory addresses. It is the CPU that takes this vector number and, using the CPU's 'interrupt vector table' [IVT], uses the vector number as an index into the IVT to properly vector the interrupt to an ISR routine.

On 80386 and later architectures, the IVT is actually called an IDT ('interrupt descriptor table'). For details, see the 'System Programming Guide', chapter 6: http://download.intel.com/design/processor/manuals/253668.pdf

As, to whether the resulting ISR address from the IVT/IDT is physical or logical depends on the processor mode (e.g. real mode, protected mode, protected with virtual addressing enabled).

In a sense, all such addresses are always logical. And, all logical addresses undergo a translation to physical on each CPU instruction. Whether the translation is one-to-one [MMU not enabled or page tables have one-to-one mapping] is a question for 'How has the OS set things up?'

Craig EsteyCraig Estey

Strictly speaking, there is no such thingas 'acknowledge an interrupt to device'.The thing that an ISR should do, is to handlethe interrupt condition. For example, ifthe UART requested an interrupt because ithas an incoming data, then you should readthat incoming data. After that read operation,UART no longer has the incoming data, so naturallyit stops asserting the IRQ line. Alternatively,if your program no longer needs to read thedata and wants to stop the communication, itwould just mask the receiver interrupt viathe UART registers, and, once again, UARTwill stop asserting the IRQ line. If the devicejust wanted to signal you some state change,then you should read the new state, and thedevice will know that you have an up-to-datestate and will release an IRQ line.

So, in short: there is usually no any device-specificacknowledge procedure. All you need to do isto service an interrupt condition, after which,that condition will disappear, voiding theinterrupt request.

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